Summary of Role :
GlobalFoundries seeks an experienced RF IP Development Engineer who will have responsibility to plan, execute, monitor, and control RF IP Development projects from requirements definition to release of the RF IP and its silicon hardware validation. This position will be located at our Burlington, VT location.
Essential Responsibilities :
Use industry-standard design tools to perform gate/transistor level electrical circuit design and physical layout, circuit design verification/simulation with electrical, physical, and timing rules generation for Foundry circuits
Working with Standard Cell Logic libraries, IO libraries, and Efuse Macros. Designing high-speed IOs (e.g. LVDS, SSTL, HSTL). Demonstrate knowledge of SOC design principles. T
The capability of running aging (Reliability) simulation tools ( e.g. RelXpert, Voltus)
Must have transistor level electrical circuit design understanding.
Must be able to interpret electrical design specifications
Applicant should have a proficient knowledge of and experience with EDA tools for schematic and physical layout, design rule checking (DRC), layout versus schematic checking (LVS, schematic and layout extraction, methodology checking, circuit simulation and analysis, and various physical and electrical rules
Knowledge of AIX/NFS, Linux, Shell, Tcl, Perl
Must have good technical verbal and written communication skills and ability to work with cross-functional teams is necessary
Candidates who are self-driven and have worked in a global team environment with a successful track record of on-time high quality IP design creation.
Be able to collaborate with program and technical design leads on multiple concurrent projects.
Should have excellent problem solving skills, written & oral communication, teaming & interpersonal skills
Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs
Required Qualifications :
Bachelor's Degree from an Accredited College and or University in Engineering or Related Technical Discipline
7 or More Years of Relevant Experience
3 or More Years of Experience with Digital/Analog IP Circuit Design, Layout, and Timing
Minimal Travel Required
Language Fluency: English (Written & Verbal)
Master's Degree from an Accredited College and or University in Engineering or Related Technical Discipline with 6 or more years of experience
PhD from Accredited College and or University in Engineering or Related Technical Discipline with 4 or more years of experience
Should have experience with various types of layout methods for transistor-level circuit design
Knowledge of the end-to-end IP and Chip design cycles
Knowledge in RF technologies (Bulk, CMOS & SOI) process is desired.
Project management, Schedule development, SOW creation skills are desired.
If you need a reasonable accommodation for any part of the employment process, please contact us by email at firstname.lastname@example.org and let us know the nature of your request and your contact information. Requests for accommodation will be considered on a case-by-case basis. Please note that only inquiries concerning a request for reasonable accommodation will be responded to from this email address.
An offer of employment with GLOBALFOUNDRIES is conditioned upon the successful completion of a background check and drug screen, as applicable and subject to applicable laws and regulations.
GLOBALFOUNDRIES is fully committed to equal opportunity in the workplace and believes that cultural diversity within the company enhances its business potential. GLOBALFOUNDRIES goal of excellence in business necessitates the attraction and retention of highly qualified people. Artificial barriers and stereotypic biases detract from this objective and may be illegally discriminatory.
Procedure: All policies and processes which pertain to employees including recruitment, selection, training, utilization, promotion, compensation, benefits, extracurricular programs, and termination are created and implemented without regard to age, ethnicity, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, sexual orientation, gender identity or expression, veteran status, or any other characteristic or category specified by local, state or federal law.
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