Principal ASIC Design Engineer *Job Title: * Principal ASIC Design Engineer
*Job Location: * Irvine, CA or San Jose, CA
*Job Salary: * $160k-$180k + Bonus + RSU's + Benefits - $200k - $350k total comp
*Requirements: * Verilog, STA, RTL, ASIC, Digital Design
We are a global tech leader in the semiconductor industry based in Irvine, CA and San Jose, CA. We have been designing, developing, and supplying semiconductor and infrastructure software solutions for the past 30 years. Due to growth we are seeking an experienced Principal ASIC Design Engineer who has 8+ years of experience with Verilog, STA, ASIC, or Digital Design.
If you are a Principal ASIC Design Engineer with Verilog and STA experience, please read on!
What You Need for this Position *Must Have Skills: *
1.) 8+ years of experience as an ASIC Design Engineer
2.) Expertise with Verilog
3.) RTL design
4.) Expertise with Primetime Static Time Analysis (STA)
5.) Bachelor's or Master's Degree in Electrical Engineering or related
What's In It for You We are a global teach leader that values our employees, if hired, you will be rewarded with an offer that will include:
1.) $160k -$180k Salary + Bonus - $200k - 350k total comp
5.) Work/Life Balance
So, if you are a Principal ASIC Design Engineer with experience, please apply today!
- Applicants must be authorized to work in the U.S.
*CyberCoders, Inc is proud to be an Equal Opportunity Employer*
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability, protected veteran status, or any other characteristic protected by law.
*Your Right to Work* - In compliance with federal law, all persons hired will be required to verify identity and eligibility to work in the United States and to complete the required employment eligibility verification document form upon hire.
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